Conventionally, integrated circuit tasks (or, jobs) in a very-large-scale-integration (VLSI) process are addressed on a first-in, first-out (FIFO) basis in a processing system. That is, tasks assigned to a first integrated circuit device (or batch of devices), which are first entered into the processing system, take precedent over tasks assigned to a second integrated circuit device (or batch of devices) later entered. This (FIFO) processing approach leads to process inefficiencies, as it is not always advantageous to process tasks in the order in which they are submitted.